Conferences
2010
With Christophe Alias, Paul Feautrier, and Laure
Gonnord. "Multi-dimensional Rankings, Program Termination, and Complexity
Bounds of Flowchart Programs", 17th International Static Analysis Symposium
(SAS'10), September 2010, Perpignan, France.
With Christophe Alias and Alexandru Plesco. "Optimizing DDR-SDRAM
Communications at C-level for Automatically-Generated Hardware Accelerators. An
Experience With the Altera C2H HLS Tool", 21st IEEE International
Conference on Application-specific Systems, Architectures and Processors
(ASAP'10), July 2010. IEEE Computer Society.
With Florent Bouchez, Quentin Colombet, Christophe Guillon, and Fabrice
Rastello. "Parallel Copy Motion", 13th International Workshop on
Software and Compilers for Embedded Systems (Scopes'10), June 2010, St. Goar,
Germany.
2009
With Benoit Boissinot, Benoît Dupont de Dinechin, Christophe Guillon, and
Fabrice Rastello. "Revisiting Out-of-SSA Translation for Correctness, Code
Quality, and Efficiency", International Symposium on Code Generation and
Optimization (CGO'09), pages 114-125, March 2009. IEEE Computer Society
Press. Best paper award.
2008
With Florent Bouchez and Fabrice Rastello. "Advanced Conservative and
Optimistic Register Coalescing", International Conference on Compilers,
Architectures and Synthesis for Embedded Systems (CASES'08), Atlanta, GA, USA,
pages 147-156, October 2008. ACM Press.
2007
With Christophe Alias and Fabrice Baray. "Bee+Cl@k: An Implementation of
Lattice-Based Array Contraction in the Source-to-Source Translator ROSE",
ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded
Systems (LCTES'07), volume 42, San Diego, USA, pages 73-82, June 2007. ACM
Press.
With Florent Bouchez and Fabrice Rastello. "On the Complexity of
Register Coalescing", International Symposium on Code Generation and
Optimization (CGO'07), pages 102-114, March 2007. IEEE Computer Society
Press. Best paper award.
With Florent Bouchez and Fabrice Rastello. "On the Complexity of Spill
Everywhere under SSA Form", ACM SIGPLAN/SIGBED Conference on Languages,
Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego,
USA, pages 103-112, June 2007. ACM Press.
With Clément Quinson. "Scheduling Register-Allocated Codes in
User-Guided High-Level Synthesis", 18th IEEE International Conference on
Application-specific Systems, Architectures and Processors (ASAP'07), pages
554-561, July 2007. IEEE Computer Society.
2006
With Florent Bouchez, Christophe Guillon, and Fabrice
Rastello. "Register Allocation: What does the NP-Completeness Proof of
Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and
How", International Workshop on Languages and Compilers for Parallel
Computing (LCPC'06), New Orleans, FL, USA, November 2006. Springer
Verlag.
With Florent Bouchez, Christophe Guillon, and Fabrice
Rastello. "Register Allocation: What does the NP-Completeness Proof of
Chaitin et al. Really Prove?", Annual Workshop in Duplicating,
Deconstructing, and Debunking (WDDD'06), held in conjunction with the
International Symposium on Computer Architecture (ISCA'33), Boston, MA, USA,
July 2006.
With Hadda Cherroun and Paul Feautrier. "Scheduling under Resource
Constraints using Dis-Equalities", Design Automation and Test in Europe
(DATE'06), March 2006.
2005
With Steven Derrien and Tanguy Risset. "Hardware-Software
Interface for Multi-Dimensional Processor Arrays", IEEE 16th
International Conference on Application-specific Systems,
Architectures and Processors, Samos, July 2005.
With Rob Schreiber. "A Linear-Time Algorithm for Optimal
Barrier Placement", ACM SIGPLAN 2005 Symposium on Principles and
Practice of Parallel Programming (PPoPP'05), Chicago, June
2005.
2003
With Rob Schreiber and Gilles Villard. "Lattice-Based Memory
Allocation", 6th ACM International Conference on Compilers,
Architectures and Synthesis for Embedded Systems (CASES'03), pages
298-308, IEEE Computer Society Press, 2003.
2002
With Guillaume Huard. "New Results on Array Contraction",
13th International Conference on Application-specific Systems,
Architectures, and Processors (ASAP'02), pages 359-370, IEEE
Computer Society Press, 2002.
With Daniel Chavarría-Miranda, Rob Fowler, and John Mellor-Crummey.
"Generalized Multipartitioning for Multi-Dimensional Arrays",
16th International Parallel and Distributed Processing Symposium
(IPDPS'02), Fort Lauderdale, Florida, IEEE Computer Society Press,
2002. Best paper award.
With Guillaume Huard. "Complexity of Multi-Dimensional Loop
Alignment", 19th International Symposium on Theoretical Aspects of
Computer Science (STACS'02), pages 179-191, LNCS volume 2285, Springer
Verlag, 2002.
2000
With Georges-André Silber. "Temporary Arrays for Distribution
of Loops with Control Dependences", European Conference on
Parallel Computing (Euro-Par'00), pages 357-367, LNCS volume 1900,
München, Germany, 2000.
With Claude Diderich, Marc Gengler, and Frédéric Vivien.
"Scheduling the Computations of a Loop Nest with Respect to a Given
Mapping", European Conference on Parallel Computing (Euro-Par'00),
LNCS volume 1900, pages 405-414, München, Germany, 2000.
With Rob Schreiber, Bob R. Rau, and Frédéric Vivien. "A
Constructive Solution to the Juggling Problem in Systolic Array
Synthesis", International Parallel and Distributed Processing
Symposium (IPDPS'00), pages 815-821, Cancun, Mexico, IEEE Computer
Society Press, 2000.
1999
"On the Complexity of Loop Fusion", International
Conference on Parallel Architectures and Compilation Techniques
(PACT'99), pages 149-157, IEEE Computer Society Press, 1999.
With Guillaume Huard. "Loop Shifting for Loop
Compaction", Languages and Compilers for Parallel Computing
(LCPC'99), pages 415-431, LNCS volume 1863, Springer Verlag, 1999.
With Georges-André Silber. "The Nestor Library: A Tool for
Implementing Fortran Source to Source Transformations", High
Performance Computing and Networking (HPCN'99), pages 653-662, LNCS
volume 1593, Springer Verlag, 1999.
1996
With Pierre-Yves Calland, Yves Robert, and Frédéric Vivien.
"Plugging Anti and Output Dependence Removal Techniques into Loop
Parallelization Algorithms", 3rd Workshop on Environments and
Tools for Parallel Scientific Computing, J. J. Dongarra and
B. Tourancheau, éditeurs, SIAM Press, 1996.
With Thomas Brandes, Serge Chaumette, Marie-Christine Counilh,
Frédéric Desprez, Jean-Christophe Mignot, and Jean Roman. "HPFIT and
the TransTool Environment", 3rd Workshop on Environments and Tools
for Parallel Scientific Computing, J. J. Dongarra and B. Tourancheau,
éditeurs, SIAM Press, 1996.
With Frédéric Vivien. "Optimal Fine and Medium Grain
Parallelism Detection in Polyhedral Reduced Dependence Graphs",
Parallel and Architectures and Compilation Techniques (PACT'96), pages
281-291, IEEE Computer Society Press, 1996.
With Frédéric Vivien. "On the Optimality of Allen and
Kennedy's Algorithm for Parallelism Detection in Nested
Loops". European Conference on Parallel Computing (Europar'96),
pages 379-388, LNCS volume 1123,
Springer Verlag, 1996.
With Pierre-Yves Calland, Yves Robert, and Frédéric Vivien. "On
the Removal of Anti and Output Dependences", Application Specific
Systems, Architectures and Processors (ASAP'96), pages 353-364,
J. Fortes, C. Mongenet, K. Parhi, and V. Taylor, éditeurs, IEEE Computer
Science Press, 1996.
With Pierre-Yves Calland and Yves Robert. "A New Guaranteed
Heuristic for the Software Pipelining Problem", International
Conference on Supercomputing (ICS'96), pages 261-296, ACM Press,
1996.
1995
With Frédéric Vivien. "A Classification of Nested Loops
Parallelization Algorithms" INRIA-IEEE Symposium on Emerging
Technologies and Factory Automation (ETFA'95), pages 217-224, IEEE
Computer Society Press, 1995.
With Vincent Bouchitté, Pierre Boulet, and Yves Robert. "Heuristics
for the Evaluation of Array Expressions on State-of-the-Art Massively
Parallel Machines", Algorithms and Parallel VLSI Architectures
III, pages 319-330, M. Moonen and F. Catthoor, éditeurs, North Holland,
1995.
With Michèle Dion and Yves Robert. "A Characterization of
One-to-One Modular Mappings", 7th IEEE Symposium on Parallel and
Distributed Processing (SPDP'95), pages 382-389, IEEE Computer Science
Press, 1995.
With Frédéric Vivien. "Revisiting the Decomposition of Karp,
Miller and Winograd", Application Specific Array Processors
(ASAP'95), pages 13-25, IEEE Computer Society Press, 1995.
1994
With Yves Robert. "The Alignment Problem for Perfect Uniform
Loop Nest: NP-Completeness and Heuristics", 2nd Workshop on
Environments and Tools for Parallel Scientific Computing, pages 33-42,
J. J. Dongarra and B. Tourancheau, éditeurs, SIAM Press, 1994.
With Vincent Bouchitté, Pierre Boulet, and Yves
Robert. "Evaluating Array Expressions on Massively Parallel
Machines with Communication/Computation Overlap", Parallel
Processing: CONPAR 94-VAPP VI, pages 713-724, B. Buchberger and
J. Volkert, éditeurs, LNCS volume 854, Springer Verlag, 1994.
With Pierre Boulet, Tanguy Risset, and Yves
Robert. "(Pen)-Ultimate Tiling", Scalable High Performance
Computing Conference (SHPCC'94), pages 568-576, IEEE Computer
Society Press, 1994.
"Mapping Uniform Loop Nests onto Distributed Memory
Architectures", Parallel Computing: Trends and Applications
(ParCo'94), pages 287-294, G. R. Joubert, D. Trystram, F. J. Peters, and
D. J. Evans, éditeurs, Elsevier Science B.V., 1994.
1993
With Tanguy Risset and Yves Robert. "Loop Nest Scheduling and
Transformations", 1st Workshop on Environments and Tools for
Parallel Scientific Computing, pages 309-332, J. J. Dongarra and
B. Tourancheau, éditeurs, volume 6 des Advances in Parallel Computing,
North Holland, 1993.
With Yves Robert. "Communication-Minimal Mapping of Uniform
Loop Nests onto Distributed Memory Architectures", Application
Specific Array Processors (ASAP'93), pages 1-14, L. Dadda and B. Wah,
éditeurs, IEEE Computer Society Press, 1993.
With Tanguy Risset and Yves Robert. "Formal
Methods for Solving the Algebraic Path Problem",
Application-Driven Architecture Synthesis, pages 47-69, F. Catthoor and
L. Svensson, éditeurs, Kluwer, 1993.
1992
With Yves Robert. "Scheduling Uniform Loop Nests", ISMM
Conference on Parallel and Distributed Systems, pages 75-82, R. Melhem,
éditeur, ISMM Press, 1992.
With Leonid Khachiyan and Yves Robert. "Linear Scheduling is
Close to Optimality". Application Specific Array Processors
(ASAP'92), pages 37-46, J. A. B. Fortes, E. Lee, and T. Meng, éditeurs,
IEEE Computer Society Press, 1992.
With Yves Robert. "Séquencement des nids de boucles",
Algorithmique Parallèle, pages 343-368, M. Cosnard, M. Nivat, and
Y. Robert, éditeurs, Masson, 1992.
"Two Heuristics for Task Scheduling", Algorithms and
Parallel VLSI Architectures, pages 383-388, P. Quinton and Y. Robert,
éditeurs, volume 2, Elsevier Science Publishers B.V., 1992.
1991
With Tanguy Risset and Yves Robert. "Systolic Systems",
2nd IEE International Specialist Seminar on Parallel Digital
Processors, pages 6-10, P. J. Hargrave, éditeur, volume 334, IEE
Press, 1991.
With Tanguy Risset and Yves Robert. "Synthesizing Systolic
Arrays: Some Recent Developments", Application Specific Array
Processors (ASAP'91), pages 372-386, M. Valero, S. Kung, T. Lang, and
J. Fortes, éditeurs, IEEE Computer Society Press, 1991.