Journal publications
With Philip Brisk, Benoit Boissinot, and Fabrice Rastello. "SSI
Properties Revisited", ACM Transactions on Embedded Computing Systems (ACM
TECS), 2010, to appear.
With Hadda Cherroun and Paul Feautrier. "Reservation Table Scheduling:
Branch-and-Bound Based Optimization vs. Integer Linear Programming
Techniques", RAIRO-OR, 41(4):427-454, December 2007.
With Rob Schreiber and Gilles Villard. "Lattice-Based Memory
Allocation", IEEE Transactions on Computers, 54(10):1242-1257, October
2005. Special issue tribute to B. Ramakrishna (Bob) Rau. IEEE_TC
With Guillaume Huard. "New Complexity Results on Array
Contraction and Related Problems", Journal of VLSI Signal
Processing-Systems for Signal, Image, and Video Technology, 40(1):35-55, 2005.
JVSP
With Daniel Chavarría-Miranda, Rob Fowler, and John
Mellor-Crummey. "Generalized Multipartitioning of Multi-Dimensional
Arrays for Parallelizing Line-Sweep Computations", Journal of
Parallel and Distributed Computing, 63(9):887-911, 2003.
JPDC
With Rob Schreiber, Bob Ramakrishna Rau, and Frédéric
Vivien. "Constructing and Exploiting Linear Schedules with
Prescribed Parallelism", ACM Transactions on Design Automation of
Electronic Systems, 7(1):159-172, 2002.
TODAES-7.1
With Guillaume Huard. "Loop Shifting for Loop
Compaction", International Journal of Parallel Programming,
28(5):499-534, 2000.
IJPP-28.5
"On the Complexity of Loop Fusion", Parallel
Computing, 26(9):1175-1193, 2000.
PARCO-26.9
"Mathematical Tools for Loop Transformations: From Systems
of Uniform Recurrence Equations to the Polytope Model", in
"Algorithms for Parallel Processing" (M.H. Heath, A. Ranade, and
R.S. Schreiber), 105:147-183, IMA Volumes in Mathematics and its
Applications, Springer Verlag, 1999.
IMA
With Pierre-Yves Calland and Yves Robert, "Circuit Retiming
Applied to Decomposed Software Pipelining", IEEE Transactions on
Parallel and Distributed Systems, 9(1):24-35, 1998.
TPDS-9.1
With Pierre Boulet, Georges-André Silber, and Frédéric Vivien,
"Loop Parallelization Algorithms: From Parallelism Extraction to
Code Generation", Parallel Computing, 24(3):421-444, 1998.
PARCO-24.3
With Pierre-Yves Calland, Yves Robert, and Frédéric
Vivien. "On the Removal of Anti and Output Dependences",
International Journal of Parallel Programming, 26(3):285-312, 1998.
IJPP-26.3
With Georges-André Silber and Frédéric Vivien, "Combining
Retiming and Scheduling Techniques for Loop Parallelization and Loop
Tiling", Parallel Processing Letters, 7(4):379-392, 1998.
PPL-7.4
With Frédéric Vivien, "Optimal Fine and Medium Grain
Parallelism Detection in Polyhedral Reduced Dependence Graphs",
International Journal of Parallel Programming, 25(6):447-496, 1997.
IJPP
With Frédéric Vivien, "Parallelizing Nested Loops with
Approximation of Distance Vectors: A Survey", Parallel Processing
Letters, 7(2):133-144, 1997.
PPL-7.2
With Pierre-Yves Calland, Yves Robert, and Frédéric
Vivien, "Plugging Anti and Output Dependence Removal Techniques
into Loop Parallelization Algorithms", Parallel Computing,
23(1):231-266, 1997.
Parco-23
With Frédéric Vivien, "On the Optimality of Allen and
Kennedy's Algorithm for Parallelism Detection in Nested Loops",
Journal of Parallel Algorithms and Applications, 12:83-112, 1997.
JPAA
With Frédéric Desprez, Jean-Christophe Mignot, and Yves Robert,
"TransTool: A Restructuring Tool for the Parallelization of
Applications using High Performance Fortran", Journal of the
Brazilian Computer Society, 3(2):5-15, 1996.
With Michčle Dion and Yves Robert, "A Characterization of
One-to-One Modular Mappings", Parallel Processing Letters,
5(1):145-157, 1996.
PPL-5.1
With Frédéric Vivien, "Revisiting the
Decomposition of Karp, Miller, and Winograd", Parallel Processing
Letters, 5(4):551-562, 1995.
PPL-5.4
With Vincent Bouchitté, Pierre Boulet, and Yves Robert,
"Evaluating Array Expressions on Massively Parallel Machines with
Communication/Computation Overlap", International Journal of
Supercomputer Applications and High Performance Computing, 9(3):205-219, 1995.
IJSCA-9.3
With Yves Robert, "Affine-by-Statement Scheduling of Uniform
and Affine Loop Nests over Parametric Domains", Journal of Parallel
and Distributed Computing, 29:43-59, 1995.
JPDC-29
With Pierre Boulet, Tanguy Risset, and Yves Robert,
"(Pen)-Ultimate Tiling?", INTEGRATION, The VLSI Journal, 17:33-51, 1994.
Integration-17
With Yves Robert, "On the Alignment Problem", Parallel
Processing Letters, 4(3):259-270, 1994.
PPL-4.3
With Yves Robert, "Constructive Methods for Scheduling
Uniform Loop Nests", IEEE Transactions on Parallel Distributed
Systems, 5(8):814-822, 1994.
TPDS-5.8
With Yves Robert, "Mapping Uniform Loop Nests onto
Distributed Memory Architectures", Parallel Computing, 20:679-710, 1994.
Parco-20
With Leonid Khachiyan and Yves Robert, "Linear Scheduling is
Nearly Optimal", Parallel Processing Letters, 1(2):73-81,
1991.
PPL-1.2
"Regular Partitioning for Synthesizing Fixed-Size Systolic
Arrays". INTEGRATION, The VLSI Journal, 12:293-304, 1991.
Integration-12