Publications

[1] Christophe Alias, Carsten Fuhs, and Laure Gonnord. Estimation of Parallel Complexity with Rewriting Techniques. In 15th International Workshop on Termination (WST'16), Obergurgl, Austria, September 2016. [ http | .pdf ]
[2] Christophe Alias, Fabrice Rastello, and Alexandru Plesco. High-Level Synthesis of Pipelined FSM from Loop Nests. Research Report 8900, INRIA, April 2016. [ http | .pdf ]
[3] Christophe Alias and Alexandru Plesco. Data-aware Process Networks. Research Report RR-8735, Inria - Research Centre Grenoble - Rhône-Alpes, June 2015. [ http | .pdf ]
[4] Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, and Yun Zou. Mono-parametric Tiling is a Polyhedral Transformation. Research Report 8802, INRIA Grenoble - Rhône-Alpes ; CNRS, October 2015. [ http | .pdf ]
[5] Guillaume Iooss, Sanjay Rajopadhye, Christophe Alias, and Yun Zou. CART: Constant aspect ratio tiling. In Sanjay Rajopadhye and Sven Verdoolaege, editors, 4th International Workshop on Polyhedral Compilation Techniques (IMPACT'14), Vienna, Austria, January 2014.
[6] Guillaume Iooss, Christophe Alias, and Sanjay Rajopadhye. On program equivalence with reductions. In 21st International Static Analysis Symposium (SAS'14), Munich, Germany, September 2014.
[7] Christophe Alias and Alexandru Plesco. Method of automatic synthesis of circuits, device and computer program associated therewith. Patent FR1453308, April 2014.
[8] Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA. In ACM SIGDA Intl. Conference on Design, Automation and Test in Europe (DATE'13), Grenoble, France, 2013.
[9] Guillaume Iooss, Christophe Alias, and Sanjay Rajopadhye. Semantic program optimization avoiding (some) data dependencies. In 8th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC'13), poster, Berlin, Germany, January 2013.
[10] Guillame Iooss, Sanjay Rajopadhye, and Christophe  Alias. Semantic tiling. In Workshop on Leveraging Abstractions and Semantics in High-performance Computing (LASH-C'13), Shenzhen, China, February 2013.
[11] Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Rank: A tool to check program termination and computational complexity. In International Workshop on Constraints in Software Testing Verification and Analysis (CSTVA'13), page 238, Luxembourg, March 2013. [ http ]
[12] Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA. In 2nd International Workshop on Polyhedral Compilation Techniques (IMPACT'12), 2012.
[13] Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing remote accesses for offloaded kernels: Application to high-level synthesis for FPGA. In 17th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming (PPoPP'12), 2012.
[14] Guillaume Andrieu, Christophe Alias, and Laure Gonnord. SToP: Scalable termination analysis of (C) programs (tool presentation). In International Workshop on Tools for Automatic Program Analysis (TAPAS'12), Deauville, France, September 2012.
[15] Guillaume Andrieu, Christophe Alias, and Laure Gonnord. Modular termination of C programs. Research Report RR-8166, INRIA, December 2012. [ http ]
[16] Christophe Alias, Bogdan Pasca, and Alexandru Plesco. FPGA-specific synthesis of loop-nests with pipeline computational cores. Microprocessors and Microsystems, 36(8):606-619, November 2012.
[17] Christophe Alias, Bogdan Pasca, and Alexandru Plesco. Automatic generation of FPGA-specific pipelined accelerators. In International Symposium on Applied Reconfigurable Computing (ARC'11), 2011.
[18] Christophe Alias, Alain Darte, and Alexandru Plesco. Kernel Offloading with Optimized Remote Accesses. Research report RR-7697, INRIA, July 2011. [ http | .pdf ]
[19] Christophe Alias, Bogdan Pasca, and Alexandru Plesco. FPGA-Specific Synthesis of Loop-Nests with Pipelined Computational Cores. Research report RR-7674, INRIA, July 2011. [ http ]
[20] Christophe Alias, Alain Darte, and Alexandru Plesco. Program Analysis and Source-Level Communication Optimizations for High-Level Synthesis. Research report RR-7648, INRIA, June 2011. [ http | .pdf ]
[21] Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing DDR-SDRAM communications at c-level for automatically-generated hardware accelerators. an experience with the altera C2H HLS tool. In IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'10), 2010.
[22] Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Multi-dimensional rankings, program termination, and complexity bounds of flowchart programs. In International Static Analysis Symposium (SAS'10), 2010.
[23] Christophe Alias, Alain Darte, and Alexandru Plesco. Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience with the Altera C2H HLS Tool. Research report RR-7281, INRIA, May 2010. [ http | .pdf ]
[24] Christophe Alias, Alain Darte, Paul Feautrier, and Laure Gonnord. Bounding the Computational Complexity of Flowchart Programs with Multi-dimensional Rankings. Research report RR-7235, INRIA, March 2010. [ http | .pdf ]
[25] Qingda Lu, Christophe Alias, Uday Bondhugula, Thomas Henretty, Sriram Krishnamoorthy, J. Ramanujam, Atanas Rountev, P. Sadayappan, Yongjian Chen, Haibo Lin, and Tin fook Ngai. Data layout transformations for enhancing data locality on NUCA chip multiprocessors. In ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'09), 2009.
[26] Christophe Alias, Alain Darte, Paul Feautrier, Laure Gonnord, and Clément Quinson. Program Termination and Worst Time Complexity with Multi-Dimensional Affine Ranking Functions. Research report, INRIA, 2009. [ http | .pdf ]
[27] Christophe Alias, Fabrice Baray, and Alain Darte. Bee+cl@k : An implementation of lattice-based array contraction in the source-to-source translator rose. In ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), 2007.
[28] Silvius Rus, Guobin He, Christophe Alias, and Lawrence Rauchwerger. Region array ssa. In ACM/IEEE International Conference on Parallel Architectures and Compilation Techniques (PACT'06), 2006.
[29] Christophe Alias. Program Optimization by Template Recognition and Replacement. PhD thesis, Université de Versailles, 2005.
[30] Christophe Alias and Denis Barthou. Deciding where to call performance libraries. In European Conference on Parallel Processing (Euro-Par'05), 2005.
[31] Christophe Alias and Denis Barthou. On domain specific languages re-engineering. In IEEE/ACM International Conference on Generative Programming and Component Engineering (GPCE'05), 2005.
[32] Christophe Alias. Tema : an efficient tool to find high-performance library patterns in source code. In International Workshop on Patterns in High-Performance Computing (PatHPC'05), 2005.
[33] Christophe Alias and Denis Barthou. Algorithm recognition based on demand-driven data-flow analysis. In IEEE Working Conference on Reverse Engineering (WCRE'03), 2003.
[34] Christophe Alias and Denis Barthou. On the recognition of algorithm templates. In International Workshop on Compiler Optimization meets Compiler Verification (COCV'03), 2003.

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