1. Fabrice Rastello, Amit Rao, and Santosh Pande. Optimal Task Scheduling to minimize Inter-Tile Latencies. Parallel Computing, 29(2):209-239, February 2003. Keyword(s): automatic parallelization, tiling, nested loop, reordering, pipelined communications, uniform dependances, equivalence classes, intra-tile parallelism . [bibtex-entry]

1. Thierry Dauxois and Fabrice Rastello. Efficient tiling for an ODE discrete integration program: redundant tasks instead of trapezoidal shaped-tiles. In Workshop on Massively Parallel Processing (WMPP'2002), held in conjunction with the International Parallel and Distributed Processing Symposium (IPDPS'02), pages 246--253, April 2002. IEEE Computer Society Press. Keyword(s): tiling, Hierarchical tiling, redundant tasks, automatic parallelization, scalability, cache optimization, locality, tiles shape, communication overhead, heterogeneous ressource, dynamical system theory, Fermi-Pasta-Ulam chain, Lyapunov instability analysis, phase space properties, SOR program. [bibtex-entry]



2. Fabrice Rastello, Amit Rao, and Santosh Pande. Optimal Task Scheduling to minimize Inter-Tile Latencies. In International Conference on Parallel Processing (ICPP'98), pages 172-179, 1998. IEEE Computer Society Press. Keyword(s): automatic parallelization, tiling, nested loop, reordering, pipelined communications, uniform dependances, equivalence classes, intra-tile parallelism. [bibtex-entry]



3. Fabrice Rastello and Yves Robert. Loop partitioning versus tiling for cache-based multiprocessors. In International Conference on Parallel and distributed Computing and Systems, PDCS'98, Las Vegas, pages 477-483, 1998. IASTED Press. Keyword(s): tiling, compilation, data locality, loop partitioning, cache, automatic parallelization, out-of-core algorithms, hierarchical memory systems, footprint . [bibtex-entry]



4. Frédéric Desprez, Jack Dongarra, Fabrice Rastello, and Yves Robert. Determining the idle time of a tiling: new results. In Parallel Architectures and Compilation Techniques PACT'97, pages 307-317, 1997. IEEE Computer Society Press. Keyword(s): tiling, fully permutable loops, idle time, critical path, automatic parallelization, SOR program, tiling . [bibtex-entry]

1. Fabrice Rastello, Amit Rao, and Santosh Pande. Task Ordering in Linear Tiles. Technical report RR-98-11, LIP, ENS Lyon, France, 1998. Keyword(s): automatic parallelization, tiling, nested loop, reordering, pipelined communications, uniform dependances, equivalence classes, intra-tile parallelism. [bibtex-entry]

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