Laurent Thévenoux

Inria Engineer at LIP, ENS de Lyon

I’ve been in a postdoc position at the AriC project team, LIP, ENS de Lyon, France since mid-2015 as an Inria engineer. My current research activities concern the conception of accurate, efficient, and reliable algorithms relying on the IEEE 754 floating-point arithmetic in a compilation context, notably ARM targets. In this scope, I look after the adequacy of integer and floating-point instructions as well as for the FMA exploitation. This work takes place within the Nano 2017 program headed by STMicroelectronics.

In 2014, I completed a PhD at the DALI research team of the Perpignan University on a source-to-source transformation dealing with (numerical) accuracy and (execution) time criteria. I developed a code synthesis aiming to automatically trade off between accuracy and time constraints. I thereupon worked for Numalis, a startup developing a spellchecker for calculations!

I am interested in computer arithmetics, computer architecture, compilers, performance measurements, and programming in OCaml. Below, you’ll find some highlights of 2017.


International journals with review committees

International conferences with review committees and proceedings

International conferences with abstract only

Ph.D. and Master's theses

Some slides and posters


I taught several courses during my PhD and ATER at the University of Perpignan, France (french teacher/researcher temporary position), ranging from Computer Arithmetics, to Operating Systems, to Networks, to Programming. I've given a few Operating Systems lessons in the University of Lyon 1, France, since 2016.


cohd and syhd, a source-to-source error compensation of floating-point programs and synthesis tool.

redherring, an instruction-level parallelism measurement tool based on configurable hardware model. More information and access to the code coming soon.


Feel free to contact me by email at e-mail or by phone at +33 4 72 72 82 30.