Since October 2022, I am conducting a PhD thesis at LIP, Verimag, and Aniah, on formal verification techniques of electrical properties of integrated circuits at transistor-level. I am co-advised by Matthieu Moy, Pascal Raymond, Mehdi Khosravian, and Bruno Ferres.

O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian, L. Henrio, G. Radanne. 2024. A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. In Design Automation and Test in Europe. Valencia, Spain. pp.1–6. [pdf, bib]

B. Ferres, O. Oulkaid, L. Henrio, M. Khosravian, M. Moy, G. Radanne, P. Raymond. 2023. Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. In Design Automation and Test in Europe. Antwerp, Belgium. pp.1–2. [pdf, bib]

Teaching Assistant in Lionel Rieg's course: Conception et Exploitation des Processeurs. RISC-V processor design (project). Grenoble INP – Ensimag. Spring 2024 and 2025.

Teaching Assistant in Laurence Pierre's course: Modélisation des Systèmes Numériques. Circuit design labs in VHDL (Master 2). Université Grenoble Alpes. Fall 2023 and 2024.