Conférences

2010

  • Avec Christophe Alias, Paul Feautrier et Laure Gonnord. "Multi-dimensional Rankings, Program Termination, and Complexity Bounds of Flowchart Programs", 17th International Static Analysis Symposium (SAS'10), Septembre 2010, Perpignan, France.

  • Avec Christophe Alias et Alexandru Plesco. "Optimizing DDR-SDRAM Communications at C-level for Automatically-Generated Hardware Accelerators. An Experience With the Altera C2H HLS Tool", 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'07), Juillet 2010. IEEE Computer Society.

  • Avec Florent Bouchez, Quentin Colombet, Christophe Guillon et Fabrice Rastello. "Parallel Copy Motion", 13th International Workshop on Software and Compilers for Embedded Systems (Scopes'10), Juin 2010, St. Goar, Germany.

    2009

  • Avec Benoit Boissinot, Benoît Dupont de Dinechin, Christophe Guillon et Fabrice Rastello. "Revisiting Out-of-SSA Translation for Correctness, Code Quality, and Efficiency", International Symposium on Code Generation and Optimization (CGO'09), pages 114-125, Mars 2009. IEEE Computer Society Press. Best paper award.

    2008

  • Avec Florent Bouchez et Fabrice Rastello. "Advanced Conservative and Optimistic Register Coalescing", International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'08), Atlanta, GA, USA, pages 147-156, Octobre 2008. ACM Press.

    2007

  • Avec Christophe Alias et Fabrice Baray. "Bee+Cl@k: An Implementation of Lattice-Based Array Contraction in the Source-to-Source Translator ROSE", ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 73-82, Juin 2007. ACM Press.

  • Avec Florent Bouchez et Fabrice Rastello. "On the Complexity of Register Coalescing", International Symposium on Code Generation and Optimization (CGO'07), pages 102-114, Mars 2007. IEEE Computer Society Press. Best paper award.

  • Avec Florent Bouchez et Fabrice Rastello. "On the Complexity of Spill Everywhere under SSA Form", ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'07), volume 42, San Diego, USA, pages 103-112, Juin 2007. ACM Press.

  • Avec Clément Quinson. "Scheduling Register-Allocated Codes in User-Guided High-Level Synthesis", 18th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP'07), pages 554-561, Juillet 2007. IEEE Computer Society.

    2006

  • Avec Florent Bouchez, Christophe Guillon et Fabrice Rastello. "Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove? Or Revisiting Register Allocation: Why and How", International Workshop on Languages and Compilers for Parallel Computing (LCPC'06), New Orleans, FL, USA, Novembre 2006. Springer Verlag.

  • Avec Florent Bouchez, Christophe Guillon et Fabrice Rastello. "Register Allocation: What does the NP-Completeness Proof of Chaitin et al. Really Prove?", Annual Workshop in Duplicating, Deconstructing, and Debunking (WDDD'06), held in conjunction with the International Symposium on Computer Architecture (ISCA'33), Boston, MA, USA, Juillet 2006.

  • Avec Hadda Cherroun et Paul Feautrier. "Scheduling under Resource Constraints using Dis-Equalities", Design Automation and Test in Europe (DATE'06), Mars 2006.

    2005

  • Avec Steven Derrien et Tanguy Risset. "Hardware-Software Interface for Multi-Dimensional Processor Arrays", IEEE 16th International Conference on Application-specific Systems, Architectures and Processors, Samos, Juillet 2005.

  • Avec Rob Schreiber. "A Linear-Time Algorithm for Optimal Barrier Placement", ACM SIGPLAN 2005 Symposium on Principles and Practice of Parallel Programming (PPoPP'05), Chicago, Juin 2005.

    2003

  • Avec Rob Schreiber et Gilles Villard. "Lattice-Based Memory Allocation", 6th ACM International Conference on Compilers, Architectures and Synthesis for Embedded Systems (CASES'03), pages 298-308, IEEE Computer Society Press, 2003.

    2002

  • Avec Guillaume Huard. "New Results on Array Contraction", 13th International Conference on Application-specific Systems, Architectures, and Processors (ASAP'02), pages 359-370, IEEE Computer Society Press, 2002.

  • Avec Daniel Chavarría-Miranda, Rob Fowler et John Mellor-Crummey. "Generalized Multipartitioning for Multi-Dimensional Arrays", 16th International Parallel and Distributed Processing Symposium (IPDPS'02), Fort Lauderdale, Florida, IEEE Computer Society Press, 2002. Best paper award.

  • Avec Guillaume Huard. "Complexity of Multi-Dimensional Loop Alignment", 19th International Symposium on Theoretical Aspects of Computer Science (STACS'02), pages 179-191, LNCS volume 2285, Springer Verlag, 2002.

    2000

  • Avec Georges-André Silber. "Temporary Arrays for Distribution of Loops with Control Dependences", European Conference on Parallel Computing (Euro-Par'00), pages 357-367, LNCS volume 1900, München, Germany, 2000.

  • Avec Claude Diderich, Marc Gengler et Frédéric Vivien. "Scheduling the Computations of a Loop Nest with Respect to a Given Mapping", European Conference on Parallel Computing (Euro-Par'00), LNCS volume 1900, pages 405-414, München, Germany, 2000.

  • Avec Rob Schreiber, Bob R. Rau et Frédéric Vivien. "A Constructive Solution to the Juggling Problem in Systolic Array Synthesis", International Parallel and Distributed Processing Symposium (IPDPS'00), pages 815-821, Cancun, Mexico, IEEE Computer Society Press, 2000.

    1999

  • "On the Complexity of Loop Fusion", International Conference on Parallel Architectures and Compilation Techniques (PACT'99), pages 149-157, IEEE Computer Society Press, 1999.

  • Avec Guillaume Huard. "Loop Shifting for Loop Compaction", Languages and Compilers for Parallel Computing (LCPC'99), pages 415-431, LNCS volume 1863, Springer Verlag, 1999.

  • Avec Georges-André Silber. "The Nestor Library: A Tool for Implementing Fortran Source to Source Transformations", High Performance Computing and Networking (HPCN'99), pages 653-662, LNCS volume 1593, Springer Verlag, 1999.

    1996

  • Avec Pierre-Yves Calland, Yves Robert et Frédéric Vivien. "Plugging Anti and Output Dependence Removal Techniques into Loop Parallelization Algorithms", 3rd Workshop on Environments and Tools for Parallel Scientific Computing, J. J. Dongarra et B. Tourancheau, éditeurs, SIAM Press, 1996.

  • Avec Thomas Brandes, Serge Chaumette, Marie-Christine Counilh, Frédéric Desprez, Jean-Christophe Mignot et Jean Roman. "HPFIT and the TransTool Environment", 3rd Workshop on Environments and Tools for Parallel Scientific Computing, J. J. Dongarra et B. Tourancheau, éditeurs, SIAM Press, 1996.

  • Avec Frédéric Vivien. "Optimal Fine and Medium Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs", Parallel and Architectures and Compilation Techniques (PACT'96), pages 281-291, IEEE Computer Society Press, 1996.

  • Avec Frédéric Vivien. "On the Optimality of Allen and Kennedy's Algorithm for Parallelism Detection in Nested Loops". European Conference on Parallel Computing (Europar'96), pages 379-388, LNCS volume 1123, Springer Verlag, 1996.

  • Avec Pierre-Yves Calland, Yves Robert et Frédéric Vivien. "On the Removal of Anti and Output Dependences", Application Specific Systems, Architectures and Processors (ASAP'96), pages 353-364, J. Fortes, C. Mongenet, K. Parhi et V. Taylor, éditeurs, IEEE Computer Science Press, 1996.

  • Avec Pierre-Yves Calland et Yves Robert. "A New Guaranteed Heuristic for the Software Pipelining Problem", International Conference on Supercomputing (ICS'96), pages 261-296, ACM Press, 1996.

    1995

  • Avec Frédéric Vivien. "A Classification of Nested Loops Parallelization Algorithms" INRIA-IEEE Symposium on Emerging Technologies and Factory Automation (ETFA'95), pages 217-224, IEEE Computer Society Press, 1995.

  • Avec Vincent Bouchitté, Pierre Boulet et Yves Robert. "Heuristics for the Evaluation of Array Expressions on State-of-the-Art Massively Parallel Machines", Algorithms and Parallel VLSI Architectures III, pages 319-330, M. Moonen et F. Catthoor, éditeurs, North Holland, 1995.

  • Avec Michèle Dion et Yves Robert. "A Characterization of One-to-One Modular Mappings", 7th IEEE Symposium on Parallel and Distributed Processing (SPDP'95), pages 382-389, IEEE Computer Science Press, 1995.

  • Avec Frédéric Vivien. "Revisiting the Decomposition of Karp, Miller and Winograd", Application Specific Array Processors (ASAP'95), pages 13-25, IEEE Computer Society Press, 1995.

    1994

  • Avec Yves Robert. "The Alignment Problem for Perfect Uniform Loop Nest: NP-Completeness and Heuristics", 2nd Workshop on Environments and Tools for Parallel Scientific Computing, pages 33-42, J. J. Dongarra et B. Tourancheau, éditeurs, SIAM Press, 1994.

  • Avec Vincent Bouchitté, Pierre Boulet et Yves Robert. "Evaluating Array Expressions on Massively Parallel Machines with Communication/Computation Overlap", Parallel Processing: CONPAR 94-VAPP VI, pages 713-724, B. Buchberger et J. Volkert, éditeurs, LNCS volume 854, Springer Verlag, 1994.

  • Avec Pierre Boulet, Tanguy Risset et Yves Robert. "(Pen)-Ultimate Tiling", Scalable High Performance Computing Conference (SHPCC'94), pages 568-576, IEEE Computer Society Press, 1994.

  • "Mapping Uniform Loop Nests onto Distributed Memory Architectures", Parallel Computing: Trends and Applications (ParCo'94), pages 287-294, G. R. Joubert, D. Trystram, F. J. Peters et D. J. Evans, éditeurs, Elsevier Science B.V., 1994.

    1993

  • Avec Tanguy Risset et Yves Robert. "Loop Nest Scheduling and Transformations", 1st Workshop on Environments and Tools for Parallel Scientific Computing, pages 309-332, J. J. Dongarra et B. Tourancheau, éditeurs, volume 6 des Advances in Parallel Computing, North Holland, 1993.

  • Avec Yves Robert. "Communication-Minimal Mapping of Uniform Loop Nests onto Distributed Memory Architectures", Application Specific Array Processors (ASAP'93), pages 1-14, L. Dadda et B. Wah, éditeurs, IEEE Computer Society Press, 1993.

  • Avec Tanguy Risset et Yves Robert. "Formal Methods for Solving the Algebraic Path Problem", Application-Driven Architecture Synthesis, pages 47-69, F. Catthoor et L. Svensson, éditeurs, Kluwer, 1993.

    1992

  • Avec Yves Robert. "Scheduling Uniform Loop Nests", ISMM Conference on Parallel and Distributed Systems, pages 75-82, R. Melhem, éditeur, ISMM Press, 1992.

  • Avec Leonid Khachiyan et Yves Robert. "Linear Scheduling is Close to Optimality". Application Specific Array Processors (ASAP'92), pages 37-46, J. A. B. Fortes, E. Lee et T. Meng, éditeurs, IEEE Computer Society Press, 1992.

  • Avec Yves Robert. "Séquencement des nids de boucles", Algorithmique Parallèle, pages 343-368, M. Cosnard, M. Nivat et Y. Robert, éditeurs, Masson, 1992.

  • "Two Heuristics for Task Scheduling", Algorithms and Parallel VLSI Architectures, pages 383-388, P. Quinton et Y. Robert, éditeurs, volume 2, Elsevier Science Publishers B.V., 1992.

    1991

  • Avec Tanguy Risset et Yves Robert. "Systolic Systems", 2nd IEE International Specialist Seminar on Parallel Digital Processors, pages 6-10, P. J. Hargrave, éditeur, volume 334, IEE Press, 1991.

  • Avec Tanguy Risset et Yves Robert. "Synthesizing Systolic Arrays: Some Recent Developments", Application Specific Array Processors (ASAP'91), pages 372-386, M. Valero, S. Kung, T. Lang et J. Fortes, éditeurs, IEEE Computer Society Press, 1991.