COMPAS’25 Tutorial - CVA6 SoC customization

In this tutorial, we will learn how to add MMIO peripherals to an SoC orchestrated around the RISC-V CVA6. For that, we will use FPGA (Field Programmable Gate Array), a class of reprogrammable chips that can be user-configured at the logic gate level to create application-specific design or (as in our case), general-purpose cores called softcores.

The objective of this tutorial is to experiment the different levels of customization required to have functional devices:

• architectural level (addition of the controller and mapping of its addresses on the CPU’s communication bus)
• physical level (mapping of the design’s wires to the board’s communication interfaces)
• firmware level (modification of the device tree / software interfaces)

This tutorial is decomposed in 6 steps:

0. Setup

1. Introduction - Presentation of the boards / adapters

2. Software Ecosystem

3. Modifying the design

4. SD Card & UART

5. JTAG & GDB

6. Board components: LED & Buttons

A1. Bonus: ZCU104

A2. Bonus: Linux Image