Since October 2022, I am conducting a PhD thesis at LIP, VERIMAG, and Aniah — where I work under the supervision of Matthieu Moy, Pascal Raymond, Mehdi Khosravian, and Bruno Ferres on developing formal verification techniques for electrical rule checking of integrated circuits.

O. Oulkaid, B. Ferres, M. Moy, P. Raymond, M. Khosravian, L. Henrio, G. Radanne. A Transistor Level Relational Semantics for Electrical Rule Checking by SMT Solving. In Design Automation and Test in Europe (DATE) 2024. [pdf, bib]

B. Ferres, O. Oulkaid, L. Henrio, M. Khosravian, M. Moy, G. Radanne, P. Raymond. Electrical Rule Checking of Integrated Circuits using Satisfiability Modulo Theory. In Design Automation and Test in Europe (DATE) 2023. [pdf, bib]

Teaching Assistant in Lionel Rieg's course: Conception et Exploitation des Processeurs. Grenoble INP - Ensimag. Spring 2024.

Teaching Assistant in Laurence Pierre's course: Modélisation des Systèmes Numériques. Université Grenoble Alpes. Fall 2023 and Fall 2024.