2  Presentation

The aim of the SYNTOL project is to build a tool for high level synthesis of compute intensive embedded systems (or parts thereof).

The steps in synthesis are:

• The system is specified using the CRP language, an extension of C with processes, channels and ports.
• The source specification is parsed.
• The dependences in the specification are computed, including the dependences related to message passing throught channels.
• A schedule is computed. The scheduler handles:
  • Loops, arrays, channels.
  • Multi-dimensional schedules.
  • Arbitrary delays, according to the statement and the type of dependence.
  • Finite channel sizes.
  • Throughput and latency constraints.
  • Arbitrary constraints on the schedule shape (Not Yet Implemented).
  • Resource Constraints (Not Yet Implemented).
  • Memory Shrinking (Not Yet Implemented).
• A VHDL specification is deduced from the schedule and other information (Not Yet Implemented). The specification is in two parts: the behavioral specification of a control automaton, and a structural description of a datapath.
• The specification is submitted to a FPGA synthesizer.