CR 16 - Advanced Compilers: Automatic Parallelization and High-level Synthesis

Christophe Alias (CR Inria, contact person), Fabrice Rastello (DR Inria)



Since the end of Dennard scaling, processor architectures rely more and more on parallelism to gain performances. Implementing and debugging parallel programs is bug prone and the programmer want to rely as much as possible on the compiler to automate this task. This course is about automatic parallelization, the process of translating automatically a sequential program to a parallel program. Automatic parallelization raises many challenges: How to represent the computation? How much parallelism? Which parallelism? Which resource allocation? How to generate the target code/circuit? This course will present the current challenges, trends and state-of-the-art parallelizing technologies, with a special focus on high-level circuit synthesis for FPGA, a fondamental application of automatic parallelization.

Part 1: Static Parallelization
  1. Introduction
  2. Polyhedral Model
  3. Topics in High-Level Synthesis for FPGA
Part 2: Static/Dynamic Parallelization
  1. Hybrid analysis
  2. Sparse data-flow analysis
  3. Data-movement complexity analysis


Homework/research paper analysis

Step 1: Choose a paper (deadline: asap). choose a paper among the following and notify C. Alias (mail above) asap:

Step 2: Report (deadline: january 12). Write a small report (3-4 pages) using the LaTeX template here. Send your report to Christophe Alias and Fabrice Rastello (mail above).

Step 3: Slides (deadline: january 12). Prepare a presentation (15 minutes + 5 minutes questions). The timing is strict, overlasting presentations will be stopped as for any conference presentation. A good rule of thumb is to spend 1-2 minutes per slide. Hence 10 slides should be a maximum. Send your slides to Christophe Alias and Fabrice Rastello (mail above).

Step 4: Presentation. Friday 13 january, 14:00 - 17:00, amphi B.